A typical programmable logic device (PLD) includes a number of programmable logic blocks (e.g., also referred to in the art as configurable logic blocks, logic array blocks, programmable function blocks, or programmable function units). A drawback of the conventional PLD is that the programmable logic block architecture is often not optimized for the desired application. For example, the programmable logic blocks are generally homogeneous with each having the same one or two slices or each having the same block structure (e.g., a number of lookup tables (LUTs) in a single block). Consequently, the programmable logic block architecture is not optimized for the desired application and results in unused resources, larger than necessary die size, and inefficient scaling for providing a larger number of LUTs within the PLD.
Another drawback of the conventional PLD is that the routing architecture (e.g., interconnect) is often optimized for performance on a per-LUT basis for its input/output ports. Consequently, the routing architecture, which may constitute a significant percentage of the die area and affect performance, power dissipation, and overall logic utilization of the PLD, may not be optimized for scalability to higher density PLD sizes in an area efficient manner and provide the desired routing flexibility. As a result, there is a need for improved programmable logic block and routing architectures for PLDs.